For example, each of FIGS. 4 and 5 of Non-Patent Document 1 shows an amplifier circuit and a TIA having a negative feedback configuration including a feedback resistance between an input and an output of this amplifier circuit. In FIG. 5, this amplifier circuit is configured by three stages formed of a grounded-gate amplifier stage, a grounded-source amplifier stage, and a source follower stage. Also, FIG. 4 shows a method of setting a circuit parameter for decreasing noise in the grounded-gate amplifier stage, and FIG. 5 shows a system of enhancing a bandwidth by using an inductance for a load element of the grounded-gate amplifier stage or the grounded-source amplifier stage.
FIG. 2 of Non-Patent Document 2 shows a TIA having an open-loop configuration. This TIA has a configuration including amplifier stages formed of a grounded-gate amplifier stage in an initial stage and a grounded-source amplifier stage and the grounded-gate amplifier stage in a latter stage, in which the grounded-gate amplifier stage in the latter stage is gain-boosted by the grounded-source amplifier stage. Each MOS transistor is formed so as to have a large gate width, so that its bandwidth is improved.    Non-Patent Document 1: Chih-Fan Liao, Shen-Iuan Liu “40 Gb/s Transimpedance-AGC Amplifier and CDR Circuit for Broadband Data Receivers in 90 nm CMOS”, IEEE Journal of Solid-State Circuits, Vol. 43, No. 3, March 2008, p. 642-648    Non-Patent Document 2: C. Kromer and other five, “A 40 Gb/s Optical Receiver in 80-nm CMOS for Short-Distance High-Density Interconnects”, IEEE Asian Solid-State Circuits Conference 2006 (ASSCC 2006), November 2006, p. 395-398